The global semiconductor race is rapidly converging on the 2nm threshold, a critical frontier where computational efficiency dictates leadership in the realm of artificial intelligence. TSMC, maintaining its position as the world's preeminent foundry, is entering a phase of aggressive capacity expansion. This strategy encompasses more than mere quantitative growth; it represents a profound geographical diversification of assets. The current investment cycle is laying the groundwork for the computational infrastructure that will define the next decade.
The transition to the 2nm process has emerged as a strategic imperative for TSMC, even though revenue from this segment currently accounts for a mere 3% of total earnings. However, the trajectory of capacity deployment signals a massive scale-up: by mid-next year, output is projected to increase by 22%, enabling the company to process between 90,000 and 110,000 silicon wafers per month.
Simultaneously, the 3nm segment continues its aggressive expansion. While its growth rate appears more modest in percentage terms—approximately 16%—the absolute figures reveal a significant surge, with volume climbing from 180,000 to 210,000 wafers per month. To put this progress into perspective, data from Wedbush Securities shows that in the previous half-year, 3nm lines did not exceed 150,000 wafers, while cutting-edge 2nm products were processed in volumes under 60,000 units.
TSMC’s geographic strategy is now transcending its Taiwanese roots, evolving into a truly global network. In the near term, 3nm chip production will be deployed across three key hubs: Taiwan, Japan, and Arizona. Notably, at its Taiwanese facilities, the company is employing an optimization strategy by retrofitting existing lines that previously specialized in 5nm components. The fiscal magnitude of these transformations is staggering: capital expenditures for the current year are expected to reach between $60 billion and $64 billion, with the vast majority—70% to 80%—dedicated specifically to the development of advanced process nodes.
However, fabricating the die is only half the battle. The industry's primary bottleneck has shifted toward packaging and testing, particularly regarding CoWoS (Chip-on-Wafer-on-Substrate) technology, which allows multiple dies to be integrated into a single high-performance module. TSMC is aggressively expanding its capabilities in this area, focusing on the AP7 site in Taiwan while establishing a parallel facility in Arizona. The latter is critical for logistics: onshoring packaging operations in the U.S. eliminates the need to ship semi-finished products back and forth to Taiwan, significantly compressing the production cycle.
The growth forecasts for CoWoS reflect an ambitious trajectory: if packaging capacity reaches the equivalent of 130,000 wafers per month by the end of this year, that figure is expected to double to 260,000 by 2028.
Against this backdrop, the competitive challenge from Intel is beginning to take shape. With its EMIB-T technology, Intel is attempting to carve out a niche in high-tech packaging, planning to scale its volume from the current 20,000 to 45,000 wafers per month by 2028. Despite the substantial gap in scale compared to TSMC, such capabilities may become highly attractive to industry giants like Google, Amazon, and MediaTek, as they seek to diversify their supply chains and mitigate single-source dependency.
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