The relentless pursuit of semiconductor miniaturization has reached a critical threshold where the laws of classical physics no longer apply. As component dimensions shrink toward the atomic scale, the industry is colliding with fundamental quantum constraints. Today's "nanometer" process nodes are increasingly becoming marketing shorthand, masking the profound physical complexities beneath the surface. However, a novel methodology for calculating the quantum limit is now empowering engineers to design devices with precision, effectively overcoming the persistent barrier of current leakage.
Modern microelectronics is currently mired in a prolonged crisis of nomenclature. The industry's transition toward so-called 2nm process nodes has exposed a profound disconnect between marketing labels and the actual geometry of transistors. In reality, the figures used to name these nodes have long ceased to represent gate length or any specific physical dimension; instead, they have evolved into shorthand for a generation of transistor density. Yet, despite this semantic fluidity, the laws of physics remain uncompromising: current-control elements have drifted perilously close to quantum mechanical limits.
The primary obstacle to further miniaturization is a phenomenon known as quantum tunneling. In the realm of classical physics, an electron lacking sufficient energy cannot breach a potential barrier. However, at the nanometer scale, particles begin to exhibit wave-like behavior, allowing them to literally "leak" through barriers that should be impenetrable. For a transistor, this is catastrophic: parasitic leakage currents surge, and the ability to control the flow of electrons between the source and the drain deteriorates rapidly.
Empirically mapping the boundaries of this phenomenon is exceptionally difficult. The contact area between the metal electrode and the semiconductor channel is atomic in scale, making real-time, precise control of geometry and electronic structure nearly impossible. Consequently, engineers often rely on a trial-and-error approach—a methodology that is prohibitively expensive in the context of modern fabrication.
To shift the design process from the realm of conjecture to the realm of precise calculation, researchers from the Korea Advanced Institute of Science and Technology (KAIST) have proposed the use of Density Functional Theory (DFT). This powerful tool of quantum physics is traditionally employed to model the electronic structures of molecules and complex materials. By adapting DFT for the analysis of semiconductor devices, the scientists have gained the ability to predict the scaling limits of future chips with high precision, well before they reach the physical fabrication stage.
Molybdenum disulfide ($\text{MoS}_2$)—a two-dimensional semiconductor and a leading candidate for the base material in next-generation transistors—was selected as the testbed for this methodology. Due to its atomic thickness, $\text{MoS}_2$ enables the creation of structures that are theoretically far smaller than those possible with traditional silicon. The researchers analyzed the interaction of this material with various metals—scandium, silver, gold, and palladium—testing two distinct configurations: top and edge contacts.
The simulation results led to a pivotal conclusion: the critical tunneling length is not a constant. It depends directly on the metal's work function—the energy required for an electron to leave the electrode surface—as well as the geometry of the contact itself. This implies that the "quantum wall" can be pushed back through the strategic selection of materials and the method of their integration with the 2D channel.
According to the calculations, with the optimal combination of metal and contact structure, the actual (non-marketing) tunneling length can be reduced to less than 4 nm. For n-type transistors, a top-contact scheme paired with low-work-function metals proved most effective, while p-type transistors were optimized using edge contacts with high-work-function metals.
This research does not suggest that mass-market chips with these parameters will appear tomorrow. However, it provides the industry with a fundamentally new tool. Rather than relying on the costly and sluggish iteration of physical prototypes, engineers can now evaluate contact resistance and leakage regimes at the atomic level, transforming the pursuit of miniaturization into a calculated engineering discipline.
Propellantless Magnetic Pulse
