The semiconductor industry is rapidly hitting the physical wall of traditional 2D miniaturization. As the proximity between transistors reaches a critical threshold, electrical interference and current leakage begin to overshadow performance gains. To overcome this bottleneck, Samsung engineers have introduced a concept for the full-scale vertical stacking of logic elements—a technological leap that paves the way for a new generation of silicon capable of radically amplifying the computational power of AI systems.
The modern computing landscape is currently constrained by the limits of Moore's Law. For decades, progress was driven by the relentless shrinking of transistors on a two-dimensional plane, but this approach has reached a critical impasse. As components are packed closer together, insulation layers thin to the point where they can no longer effectively block electrical interference, leading to inevitable system failures. The only viable escape from this crisis is a leap into the third dimension: migrating logic elements from a flat plane into vertical structures.
Engineers from the Logic TD division at Samsung Electronics' Semiconductor Research Center have unveiled a solution that could redefine the industry. At the VLSI Symposium 2026, the company introduced the industry's first industrially viable Three-Dimensional Stacked Field-Effect Transistor (3DSFET). The breakthrough centers on a record-breaking gate pitch of just 42nm, successfully surpassing the previous industry benchmark of 48nm.
Conceptually, this approach leverages the success already seen in V-NAND and HBM memory, where data is stored in multi-layered "stacks." However, translating this architecture to logic circuits proved significantly more complex. In Samsung's new implementation, the number of channel nanosheets—the ultra-thin films through which current flows—has been increased to three layers on top and three on the bottom. This represents the current ceiling for stacked transistor density.
A critical focus was placed on the challenge of interlayer interconnects. Previously, the connection between upper and lower transistors followed a convoluted C-shaped path along the side, which wasted space and increased latency. Samsung has now implemented RBC (RX Bounded Contact) technology, enabling direct vertical "I-shaped" deep vias filled with metal and insulator, completely eliminating voids. To ensure the stable operation of n- and p-transistors, the company utilized Middle Dielectric Isolation (MDI)—a precision dielectric layer that reliably segregates different component types.
Test results confirm high electrical stability for both n-FET and p-FET structures, alongside acceptable parameter uniformity across the entire wafer. From a practical standpoint, this packing density allows for twice as many transistors within the same die area. Theoretically, this translates to a twofold increase in performance and a corresponding boost in energy efficiency—factors that are critical for High-Performance Computing (HPC) and the training of large-scale neural networks.
Samsung's current success is merely the first cornerstone of a new era. The next phase will involve the creation of full-scale test circuits, specifically SRAM (Static Random-Access Memory) blocks. This will allow the company to validate the performance of complex 3D logic under real-world conditions and definitively prove the viability of vertical computing.
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