The semiconductor industry is undergoing a fundamental transformation, as mature process nodes cease to be the primary drivers of growth. TSMC, the Taiwanese titan, is aggressively accelerating the migration of its capacity toward ultra-small transistor geometries. This shift is far more than a routine technical upgrade; it represents a profound strategic reallocation of resources aimed at maximizing profitability. By pivoting away from legacy infrastructure, the company is clearing the path for the era of next-generation silicon.
The contemporary semiconductor landscape is defined by a stark dichotomy between "mature" and "leading-edge" nodes. For TSMC, this boundary has become the primary driver of its corporate strategy: today, approximately three-quarters of the company's total revenue is generated by chips fabricated on 7nm processes and below. This aggressive concentration of resources on the bleeding edge of lithography is accelerating, leading to a systemic contraction in production volumes for legacy nodes.
This transition is most evident at the Fab 15A facility. Since the beginning of the year, 28nm wafer throughput at this site has plummeted by more than 25%. This decline is the result of a comprehensive site overhaul as Fab 15A pivots toward 4nm production. Because legacy equipment lacks the precision required for 4nm fabrication, TSMC is undertaking a massive replacement of its production lines. Meanwhile, the adjacent Fab 15B has already solidified its position as the primary hub for 7nm component manufacturing.
The scale of this reduction is significant: at the start of the year, the aggregate output of 28nm wafers across all applicable plants stood at approximately 200,000 units per month; by June, this figure had dropped to 150,000. Simultaneously, TSMC is fast-tracking the construction of the Fab 25 complex, which will house the ultra-modern A14 process. Work on the P1 building has already entered an active phase, underscoring the company's strategic priorities.
TSMC's overarching strategy involves a gradual migration of customers from the 28nm node to the more efficient 12nm process, while the bulk of capital expenditure is channeled into the development of A14 and 2nm technologies, as well as silicon photonics and advanced packaging. The latter is particularly critical; as transistor scaling hits its physical limits, innovations in 3D integration and optical data transmission will become the primary levers for driving performance gains.
Within the 28nm segment, a rigorous segregation based on profitability is taking place. Currently, TSMC utilizes this process primarily for the production of substrates in chiplet-based architectures, where transistor density requirements are lower than in primary compute cores. The production of discrete logic components via this technology is being phased out, effectively creating a market vacuum for other players.
Orders for standard 28nm chips are increasingly shifting toward UMC and VIS. If current trends persist, UMC is well-positioned to become the global leader in this segment while simultaneously expanding its 22nm capacity.
A pivotal role in this ecosystem is played by VIS, which maintains close capital ties with TSMC. While TSMC is systematically phasing out the 200mm wafer format in favor of 300mm standards, VIS remains focused on 200mm processing. However, VIS's new facility in Singapore has been engineered for 300mm infrastructure, allowing it to seamlessly absorb the orders migrating away from TSMC's lines. According to the long-term roadmap, up to 80% of TSMC's relevant capacity in this segment will be transferred to VIS over the next five years. Currently, VIS possesses the capacity to process up to 5 million 200mm wafers annually.
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