The global semiconductor race has reached a critical juncture where the physical constraints of silicon collide with rigid geopolitical barriers. Access to Extreme Ultraviolet (EUV) lithography has emerged as a primary lever of economic coercion, effectively isolating entire regions from the cutting edge of semiconductor fabrication. Under these pressures, China is compelled to rethink its fundamental approach to chip design and manufacturing in a bid to secure its technological sovereignty. Recent breakthroughs by Chinese researchers propose an audacious alternative: achieving 3-nanometer precision by leveraging legacy equipment through sophisticated engineering workarounds.
The modern microelectronics industry finds itself held hostage by a single technology: Extreme Ultraviolet (EUV) lithography. These systems enable the patterning of structures on silicon wafers so minute they are measured in single-digit nanometers. However, stringent export restrictions have rendered ASML's equipment an inaccessible resource for Chinese manufacturers, creating a technological impasse. In response, the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has proposed a strategic workaround: leveraging Deep Ultraviolet (DUV) lithography. While technically limited by a longer wavelength, DUV remains available domestically.
The linchpin of this strategy is the transition to Gate-All-Around (GAA) transistors. Unlike traditional architectures where the gate controls the channel from only a few sides, GAA completely envelops the channel. This radically reduces current leakage and enhances power efficiency, even when utilizing less precise lithography. This is not merely a substitute for the patterning method, but a fundamental shift in the geometry of the transistor itself.
Achieving 3nm-class nodes using DUV equipment necessitates the use of multi-patterning. While EUV can create complex patterns in a single pass, DUV forces engineers to split a single layer into multiple stages, employing a series of masks and repeated exposure cycles. Technically, this transforms production into an incredibly complex multi-layered puzzle. Each additional exposure cycle increases the probability of misalignment, inevitably leading to lower die yields and a sharp increase in the cost per chip.
Global industry trends validate the viability of GAA: Samsung has already integrated this architecture into its 3nm solutions, and TSMC is banking on it for its N2 (2nm) process. However, China's challenge is compounded by the need to simulate EUV-level precision using tools that were never designed for such purposes.
Despite theoretical success, the journey from laboratory prototype to mass production remains arduous. Creating a handful of functioning transistors is merely the first step. The real challenge lies in developing a comprehensive process stack: establishing interconnects, ensuring parameter stability across the entire wafer, and achieving commercial-grade yields. Without these, the technology remains an academic achievement, unable to compete with commercial solutions.
Parallel to the search for new lithography methods, Chinese researchers are strengthening their hardware infrastructure. In 2025, a solid-state coherent light source with a wavelength of 193 nm was unveiled. This is a critical component for DUV systems that could eventually reduce reliance on foreign suppliers and serve as the foundation for indigenous lithography scanners.
Simultaneously, Huawei Technologies is developing an alternative scaling concept known as the Tau Scaling Law. Rather than attempting to physically shrink the transistor to the 1.4nm limit, the company is focusing on increasing computational density through structural modifications and temporal scaling. The goal is ambitious: to achieve transistor density equivalent to the world's most advanced standards by 2031, achieving this through intelligent system optimization rather than sheer physical miniaturization.
Consequently, China's strategy has evolved into a multi-pronged game. While some attempt to extract maximum performance from available DUV equipment through sophisticated engineering workarounds, others seek to bypass Moore's Law entirely, shifting the focus from physical dimensions to architectural efficiency.
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