The global semiconductor industry has entered a phase of extreme technological attrition, where the battle is fought over every single angstrom. At the heart of this struggle lies High-NA EUV lithography—prohibitively expensive scanners engineered to drastically amplify transistor density and accelerate wafer throughput. Yet, raw technical superiority is now colliding with stark economic realities and the cold calculus of operational efficiency. Samsung is opting for a pragmatic path, deferring the wide-scale deployment of this technology until the era of sub-one-nanometer chips.
Modern lithography has hit a wall where traditional methodologies no longer suffice. The solution lies in the transition to High Numerical Aperture (High-NA) equipment, which enables the reduction of lithographic features beyond the 2nm threshold. However, the price of such progress is staggering: with single units costing up to $400 million, upgrading production facilities has become a formidable financial challenge, even for the world's tech titans.
For Samsung Electronics, the adoption of High-NA EUV has evolved from a purely technical hurdle into a strategic pivot. Despite initial plans to integrate these scanners during the 2nm and 1.4nm phases, the company has recalibrated its priorities. Mass production utilizing this technology is now slated for no earlier than 2030. This timeline aligns with an ambitious roadmap to master the A10 (1nm) process node, making the shift to a 0.55 NA aperture a logical and economically justifiable move for that specific period.
The company's current trajectory remains methodical: Samsung is already operating with 2nm technology, while the launch of the SF1.4 process is expected in 2029. By 2030, the plan involves transitioning to SF1.4+ and, ultimately, a full-scale one-nanometer standard. Samsung's engineers are confident that equipment with a numerical aperture of 0.33 remains sufficient until that milestone. Furthermore, the industry has yet to develop a comprehensive ecosystem of consumables and tooling necessary for High-NA to operate effectively at an industrial scale.
During this transition, fabs will employ a hybrid approach: traditional EUV lithography and its advanced High-NA counterpart will coexist, complementing one another. To mitigate risk, Samsung has already installed two of the latest ASML scanners at its Hwaseong campus; however, these are dedicated to research and development rather than mass production.
This caution is driven by the need to stabilize the financial structure of the company's foundry business. In a climate defined by the pursuit of major new clients and a drive toward profitability, a sharp spike in capital expenditure (CAPEX) for equipment could become a critical liability. Instead, Samsung is betting on alternative precision-enhancement methods, such as Atomic Layer Etching (ALE), which is being incrementally integrated into production cycles.
Against this backdrop, the strategies of competitors appear either more aggressive or equally cautious. Intel has already begun deploying High-NA EUV for its Panther Lake processor chips under the Intel 18A process, aiming to reclaim its technological leadership. TSMC, conversely, is maintaining a wait-and-see posture and does not plan a large-scale transition until 2029, believing that the A12 and A13 nodes can be realized without these prohibitively expensive scanners. Meanwhile, SK hynix is actively experimenting with High-NA in the memory segment, utilizing additional techniques such as phase-shift masks to maximize the equipment's resolution.
Ultimately, the industry is reaching a consensus: technological leaps are impossible without economic viability. The transition to a 0.55 aperture is inevitable, but for Samsung, this step will be taken only when the physical constraints of legacy systems are fully exhausted and the market is primed for the scaling of one-nanometer solutions.
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